ICS9222-01 Datasheet, PDF (3/6 Pages) Integrated Circuit Systems – Dual Memory Clock Generator

ICS9222 - 01
PLL Divider Selection and PLL Values (PLLCLK=REFCLK*A/B)
MULT_0 MULT_1 MULT_2 A B
0
0
0
41
0
0
1
92
0
1
0
61
0
1
1
91
1
0
0
83
1
0
1
16 3
1
1
0
81
1
1
1
10 1
CLK(1:0)/CL
KB(1:0) w/
REFCLK=
50MHz
Reserved
Reserved
300
450
Reserved
Reserved
400
Reserved
CLK(1:0)/CL
KB(1:0) w/
REFCLK=
66MHz
267MHz
300
400
Reserved
Reserved
356
Reserved
Reserved
Bypass and Test Mode Select
FS0
FS1
FS2
MODE
CLK (1:0)
0
0
0
Normal
CLK
0
0
1
Supplier Test Reserved
0
1
0
OE
Tristate
0
1
1
OE
Tristate
1
0
0
Bypass
Non-aligned
CLK
1
0
1
Supplier Test Reserved
1
1
0
Test
REFCLK
1
1
1
Reserved
Reserved
CLKB (1:0)
CLKB
Reserved
Tristate
Tristate
Non-aligned
CLKB
Reserved
REFCLKB
Reserved
0274C—11/14/05
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