9ZXL1950_17 Datasheet, PDF (3/18 Pages) Integrated Device Technology – 19-Output DB1900Z Low-Power Derivative with 85ohm Terminations

9ZXL1950 DATASHEET
Pin Descriptions
PIN #
1
2
PIN NAME
VDDA
GNDA
3 ^100M_133M#
4 ^vHIBW_BYPM_LOBW#
5 CKPWRGD_PD#
6 GND
7 VDDR
8 DIF_IN
9 DIF_IN#
10 ^SADR0_tri
11 SMBDAT
12 SMBCLK
13 ^SADR1_tri
14 FBOUT_NC#
15 FBOUT_NC
16 GND
17 DIF0
18 DIF0#
19 DIF1
20 DIF1#
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 DIF3
26 DIF3#
27 GND
28 VDD
29 DIF4
30 DIF4#
31 DIF5
32 DIF5#
33 VDDIO
34 GND
35 DIF6
36 DIF6#
PIN TYPE
PWR
GND
IN
LATCHE
D IN
IN
GND
PWR
IN
IN
IN
I/O
IN
IN
OUT
OUT
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
Power for the PLL core.
Ground pin for the PLL core.
DESCRIPTION
3.3V Input to select operating frequency. This pin has an internal pull-up resistor.
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as
an analog power rail and filtered appropriately.
HCSL True input
HCSL Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 propagation delay.
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
MAY 11, 2017
3 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE WITH 85OHM TERMINATIONS