9ZX21201_16 Datasheet, PDF (3/16 Pages) Integrated Device Technology – 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI

9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
Pin Description
PIN #
1
2
PIN NAME
VDDA
GND A
3 IREF
4 100M_133M#
5 H IBW_BYPM_LOBW#
6 C KPWRGD_PD#
7 GND
8 VDDR
9 D IF_IN
10 D IF_IN#
11 SMB_A0_tri
12 SMBDAT
13 SMBCLK
14 SMB_A1_tri
15 D FB_OUT#
16 D FB_OUT
17 D IF_0
18 D IF_0#
19 vOE0#
20 vOE1#
21 D IF_1
22 D IF_1#
23 GND
24 VDD
25 VDD
26 D IF_2
27 D IF_2#
28 vOE2#
29 vOE3#
30 D IF_3
31 D IF_3#
32 VDD
TYPE
PWR
PWR
OUT
IN
IN
IN
PWR
PWR
IN
IN
IN
I/ O
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
DESCR IPTION
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision
resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require
different values. See data sheet.
3.3V Input to select operating frequency
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
0.7 V Differential TR UE input
0.7 V Differential Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus
Add re ss es .
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus
Add re ss es .
Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization
with input clock to eliminate phase error.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input
clock to eliminate phase error.
0.7V differential true clock output
0.7V differential C omplementary clock output
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential C omplementary clock output
Ground pin.
Power supply, nominal 3.3V
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential C omplementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential C omplementary clock output
Power supply, nominal 3.3V
IDT^® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
3
1682D- 11/19/15