8P73S674_16 Datasheet, PDF (3/15 Pages) Integrated Device Technology – 1.8V LVPECL Clock Divider

Truth Tables
Table 3A. N Clock Divider
N1
0 (default)
0
1
1
Input
N0
0 (default)
1
0
1
Divider Value
÷1
÷2
÷4
÷8
Table 3B. nOEA Output Enable
Input
nOEA
0 (default)
1
Output
Q0
Output is enabled
Output is disabled in logic low state
Table 3C. nOEB Output Enable
Input
nOEB
0 (default)
1
Output
Q1, Q2, Q3
Outputs are enabled
Outputs are disabled in logic low state
8P73S674 DATA SHEET
REVISION 1 12/17/14
3
1.8V LVPECL CLOCK DIVIDER