89HPES48H12AG2 Datasheet, PDF (3/59 Pages) Integrated Device Technology – Low latency cut-through architecture

IDT 89HPES48H12AG2 Datasheet
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
12-Port Switch Core
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
x8/x4/x2/x1
Partition 1
Upstream Port
Partition 2
Upstream Port
Partition 3
Upstream Port
P2P
Bridge
P2P
Bridge
Partition 1 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 2 – Virtual PCI Bus
Partition 3 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1
Downstream Ports
Partition 2
Downstream Ports
Partition 3
Downstream Ports
Figure 2 Example of Usage of Switch Partitioning
SMBus Interface
The PES48H12AG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES48H12AG2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES48H12AG2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
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December 12, 2013