82V3399_16 Datasheet, PDF (3/5 Pages) Integrated Device Technology – Synchronization Management WAN PLL and Clock Generatiion for IEEE-1588

FUNCTIONAL BLOCK DIAGRAM
82V3399 SHORT FORM DATA SHEET
OUT1
MUX
Divider
OUT2
MUX
Divider
IN1
IN2
IN3
IN4
IN5
IN6
EX_SYNC1
EX_SYNC2
Input
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Priority
Priority
Priority
Priority
Priority
Priority
Selection
T4 Input
Selector
Monitors
T0 Input
Selector
T4 DPLL
T0 DPLL
T4
APLL
MUX
T4 APLL
T0
APLL
MUX
T0 APLL
Microprocessor Interface
JTAG
APLL
OSCI
OUT3
MUX
Divider
OUT4
MUX
Divider
OUT5
MUX
Divider
OUT6
MUX
Divider
Output
Auto
Divider
Auto
Divider
Figure 1. Functional Block Diagram
OUT1
OUT2
OUT3
OUT4
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
REVISION 9 01/05/16
11
SYNCHRONIZATION MANAGEMENT WAN PLL AND
CLOCK GENERATIION FOR IEEE-1588