82P33814_16 Datasheet, PDF (3/13 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet

FUNCTIONAL BLOCK DIAGRAM
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
LOS3
System Clock
SYS PLL
ToD/ Time
Accumulator
IN1(P/N)
IN2(P/N)
IN3(P/N)
IN4(P/N)
IN5
IN6
Reference
monitors
Reference
selection
Frac-N input
dividers
DPLL1 /
DCO1
DPLL2 /
DCO2
ToD/ Time
Accumulator
ex_sync module
DPLL3
I2C Master
I2C Slave,
SPI, UART
Control and
Status
Registers
JTAG
APLL1
APLL2
Figure 1. Functional Block Diagram
82P33814 Short Form Datasheet
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OUT1
OUT2
OUT3p/n
OUT4p/n
OUT5p/n
OUT6p/n
OUT7
OUT8
OutDiv
OutDiv
OUT9
OUT10
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
©2016 Integrated Device Technology, Inc.
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Revision 6, March 24, 2016