82P33810_16 Datasheet, PDF(3/13 Page) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet

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82P33810_16 Datasheet, PDF (3/13 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet

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82P33810 Short Form Datasheet

In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output

clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.

Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The

output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.

The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-

nected to either DPLL1 or DPLL3.

All 82P33810 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the

DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

FUNCTIONAL BLOCK DIAGRAM

LOS0 / XO_FREQ0

LOS1 / XO_FREQ1

LOS2 / XO_FREQ2

LOS3

IN1(CC)

IN2(CC)

IN3(P/N)

IN4(P/N)

IN5(P/N)

IN6(P/N)

IN7(P/N)

IN8(P/N)

IN9

IN10

IN11

IN12

IN13

IN14

System Clock

SYS PLL

Composite

Clocks

Reference

monitors

Reference

selection

Frac-N input

dividers

ToD/ Time

Accumulator

DPLL1 /

DCO1

DPLL2 /

DCO2

ToD/ Time

Accumulator

ex_sync module

DPLL3

I2C Master

I2C Slave,

SPI, UART

Control and

Status

Registers

JTAG

APLL1

APLL2

Figure 1. Functional Block Diagram

OutDiv

Composite

Clock

OutDiv

OUT1

OUT2

OUT3p/n

OUT4p/n

OUT5p/n

OUT6p/n

OUT7

OUT8

OUT9

OUT10

OUT11

FRSYNC_8K_1PPS

MFRSYNC_2K_1PPS

Revision 6, March 29, 2016

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