82P33731 Datasheet, PDF(3/12 Page) Integrated Circuit Systems

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82P33731 Datasheet, PDF (3/12 Pages) Integrated Circuit Systems – Composite clock inputs

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FUNCTIONAL BLOCK DIAGRAM

LOS0 / XO_FREQ0

LOS1 / XO_FREQ1

LOS2 / XO_FREQ2

LOS3

IN1(CC)

IN2(CC)

IN3(P/N)

IN4(P/N)

IN5(P/N)

IN6(P/N)

IN7(P/N)

IN8(P/N)

IN9

IN10

IN11

IN12

IN13

IN14

System Clock

SYS PLL

Composite

Clocks

APLL1

Reference

monitors

Reference

selection

Frac-N input

dividers

DPLL1

(T0)

APLL2

DPLL2

(T4)

ex_sync module

I2C Master

I2C Slave

Control and

Status

Registers

JTAG

APLL3

(VCXO)

Crystal

Figure 1. Functional Block Diagram

82P33731 Short Form Datasheet

OutDiv

Composite

Clock

OutDiv

OUT1

OUT2

OUT3p/n

OUT4p/n

OUT5p/n

OUT6p/n

OUT7

OUT8

OUT9

OUT10

OUT11p/n

OUT12p/n

FRSYNC_8K_1PPS

MFRSYNC_2K_1PPS

Revision 4, March 20, 2016

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