ADC1115S125 Datasheet, PDF (29/36 Pages) NXP Semiconductors – Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

Integrated Device Technology
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 21. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4 -
0000
not used
3
INTREF_EN
R/W
programmable internal reference enable
0
disable
1
active
2 to 0 INTREF[2:0]
R/W
programmable internal reference
000
0 dB (FS = 2 V)
001
1 dB (FS = 1.78 V)
010
2 dB (FS = 1.59 V)
011
3 dB (FS = 1.42 V)
100
4 dB (FS = 1.26 V)
101
5 dB (FS = 1.12 V)
110
6 dB (FS = 1 V)
111
reserved
Table 22. Input buffer control register (address 0010h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2 -
000000 not used
1 to 0 IB_IBIAS[1:0]
R/W
input buffer bias current
00
not used
01
medium
10
low
11
high
Table 23. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5 -
000
not used
4
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
0
CMOS
1
LVDS DDR
3
OUTBUF
R/W
output buffers enable
0
output enabled
1
output disabled (high Z)
2
OUTBUS_SWAP
R/W
output bus swapping
0
no swapping
1
output bus is swapped (MSB becomes LSB and vice versa)
ADC1115S125 3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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