IDT723656_09 Datasheet, PDF (28/39 Pages) Integrated Device Technology – CMOS TRIPLE BUS SyncFIFO

IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFO^TM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKC
tENS2
MBC
tENS2
WENC
tENH
tENH
tCLK
tCLKH tCLKL
COMMERCIAL TEMPERATURE RANGE
FFC
C0-C17
CLKA
HIGH
tDS
tDH ^tDS
tDH
Write 1
Write 2
(1)
tSKEW1
tCLK
tCLKH _tCLKL
1
EFA
CSA
W/RA
MBA
FIFO2 Empty
LOW
LOW
LOW
ENA
2
tREF
tENS2
A0-A35
tREF
tENH
tA
W1
5611 drw20
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
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