92HD90 Datasheet, PDF (278/302 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD90
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.1. SPKVOL L/R Registers
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
Bit
Label
verb F71/771 (Left)
verb F72/772 (Right)
verb 773 (Left and Right -
7:0
write only)
VOL[7:0]
Type Default
Description
RW 30
+36 to -91.5dB in 0.75dB steps
0x00 = +36dB
0x01 = +35.25dB
...
0x2F = +0.75dB
0x30 = 0dB
0x31 = -0.75dB
...
0xA9 = -90.75
0xAA to 0xFE = -91.5dB
0xFF = mute
7.29.1.2. AIC1 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
Register Address
Bit
Label
7
SCLKINV
verb F76/776
6
MS
5
LRSWAP
4
LRP
3:2 WL[1:0]
1:0 FORMAT[1:0]
Type Default
Description
RW 0
0 =SCLK not inverted (data and LRCLK transition on falling
edge of SCLK)
1 = invert SCLK (data and LRCLK transition on rising edge of
SCLK)
RW 1
Master/Slave
0 = SCLK and LRCLK are inputs (slave mode)
1 = SCLK and LRCLK are outputs (master mode)
RW 0
Swap Left and Right Samples
0 = Left sample first in frame
1 = Right sample first in frame
RW 0
Left/Right (I2S_LRCLK) Polarity
0 = default per format
1 = LRCLK inverted
RW 10
Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = Reserved
RW 10
link format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = reserved
IDT CONFIDENTIAL
278
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD90