5P49V5913_16 Datasheet, PDF (26/37 Pages) Integrated Device Technology – Programmable Clock Generator

5P49V5913 DATASHEET
CLKIN Equivalent Schematic
Wiring the Differential Input to Accept Single-Ended Levels
Figure Recommended Schematic for Wiring a Differential
Input to Accept Single-ended Levels shows how a differential
input can be wired to accept single ended levels. This
configuration has three properties; the total output impedance
of Ro and Rs matches the 50 ohm transmission line
impedance, the Vrx voltage is generated at the CLKIN inputs
which maintains the LVCMOS driver voltage level across the
transmission line for best S/N and the R1-R2 voltage divider
values ensure that Vrx p-p at CLKIN is less than the maximum
value of 1.2V.
V DD
Ro
Rs
Zo = 50 Ohm
Ro + Rs = 5 0
LV CMOS
R1
Vrx
R2
CLKI N
CLKI NB
Vers aCloc k 5 Rec eiver
Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
PROGRAMMABLE CLOCK GENERATOR
26
NOVEMBER 11, 2016