P9030-0NTGI8 Datasheet, PDF (25/28 Pages) Integrated Device Technology – Single Chip Wireless Power Transmitter IC for TX-A1

instability as well as EMI problems. Therefore, use
wide and short traces for high current paths.
- The 0.1μF decoupling capacitors must be mounted on
the component side of the board as close to the VDD
pin as possible. Do not use vias between decoupling
capacitors and VDD pins. Keep PCB traces to each
VDD pin and to ground vias as short as possible.
- To optimize board layout, place all components on
the same side of the board and limit the use of vias.
Route other signal traces away from the IDTP9030.
For example, use keepouts for signal traces routing
on inner and bottom layers underneath the device.
- The NQG48 6.0 mm x 6x0 mm x 75mm 48L package
has an inner thermal pad which requires blind
assembly. It is recommended that a more active flux
solder paste be used such as Alpha OM-350 solder
paste
from
Cookson
Electronics
(http://www.cooksonsemi.com). Please contact IDT
for Gerber files that contain recommended solder
stencil design.
- The package center exposed pad (EP) must be
reliably soldered directly to the PCB. The center land
pad on the PCB (set 1:1 with EP) must also be tied to
the board ground plane, primarily to maximize thermal
performance in the application. The ground
connection is best achieved using a matrix of PTH
vias embedded in the PCB center land pad for the
NTG48. The PTH vias perform as thermal conduits to
the ground plane (thermally, a heat spreader) as well
as to the solder side of the board. There, these
thermal vias embed in a copper fill having the same
dimensions as the center land pad on the component
side. Recommendations for the via finished hole-size
and array pitch are 0.3mm to 0.33mm and 1.3mm,
respectively.
- Layout and PCB design have a significant influence
on the power dissipation capabilities of power
management ICs. This is due to the fact that the
surface mount packages used with these devices rely
heavily on thermally conductive traces or pads to
transfer heat away from the package. Appropriate PC
layout techniques must then be used to remove the
heat due to device power dissipation. The following
general guidelines will be helpful in designing a board
layout for lowest thermal resistance:
1. PC board traces with large cross sectional
areas remove more heat. For optimum
IDTP9030
Product Datasheet
results, use large area PCB patterns with
wide and heavy (2 oz.) copper traces, placed
on the top layer of the PCB.
2. In cases where maximum heat dissipation is
required, use double-sided copper planes
connected with multiple vias.
3. Thermal vias are needed to provide a
thermal path to the inner and/or bottom
layers of the PCB to remove the heat
generated by device power dissipation.
4. Where possible, increase the thermally
conducting surface area(s) openly exposed
to moving air, so that heat can be removed
by convection (or forced air flow, if
available).
5. Do not use solder mask or place silkscreen
on the heat-dissipating traces/pads, as they
increase the net thermal resistance of the
mounted IC package.
Power Dissipation/Thermal Requirements
The IDTP9030 is offered in a TQFN-48L package. The
maximum power dissipation capability is 2W, limited by
the die’s specified maximum operating junction
temperature, Tj, of 125°C. The junction temperature rises
with the device power dissipation based on the package
thermal resistance. The package offers a typical thermal
resistance, junction to ambient (JA), of 31°C/W when the
PCB layout and surrounding devices are optimized as
described in the PCB Layout Considerations section. The
techniques as noted in the PCB Layout section need to be
followed when designing the printed circuit board layout,
as well as the placement of the IDTP9030 IC package in
proximity to other heat generating devices in a given
application design. The ambient temperature around the
power IC will also have an effect on the thermal limits of
an application. The main factors influencing θJA (in the
order of decreasing influence) are PCB characteristics,
die/package attach thermal pad size, and internal package
construction. Board designers should keep in mind that
the package thermal metric θJA is impacted by the
characteristics of the PCB itself upon which the TQFN is
mounted. For example, in a still air environment, as is
often the case, a significant amount of the heat that is
generated (60 - 85%) sinks into the PCB. Changing the
design or configuration of the PCB changes impacts the
overall thermal resistivity and, thus, the board’s heat
sinking efficiency.
Revision 1.0.2
25
© 2012 Integrated Device Technology, Inc.