IDTSSTE32882HLBAKG Datasheet, PDF(25/73 Page) Integrated Device Technology – 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

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IDTSSTE32882HLBAKG Datasheet, PDF (25/73 Pages) Integrated Device Technology – 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

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SSTE32882HLB

1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE

Capacitance Values

Symbol

Parameter

Conditions

Min

Typ Max Unit

Input capacitance, Data inputs

see footnote1

1.5

Input capacitance, CK, CK, FBIN,

FBIN

see footnote1

Input capacitance, CK, CK, FBIN,

see footnote1

FBIN

1.5

(1.35 V operation)

Output capacitance, Re-driven and

QxA0..QxA15, QxBA0..QxBA2, QxCS0/1,

CO Clock Outputs

QxCKE0/1, QxODT0/1, QxRAS, QxCAS,

QxWE, Y0, Y0.. Y3, Y3

CIï Delta capacitance over all inputs

CIR

Input capacitance, RESET, MIRROR, VI = VDD or GND; VDD = 1.5 V

QCSEN

2.5

0.5

1 This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according

to JEP147 ("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)")

with VDD, VSS, AVDD, AVSS, PVDD, PVSS, VREF applied and all other pins (except the pin under test) floating. Input capacitance

are measured with the device default settings when MIRROR=Low.

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