8T49N281 Datasheet, PDF (25/63 Pages) Integrated Device Technology – Operating modes: locked to input signal

8T49N281 DATA SHEET
Table 6K. Output Clock Source Control Register Bit Field Locations and Descriptions
Output Clock Source Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
00A8
Rsvd
Rsvd
PLL_SYN
0
0
00A9
Rsvd
CLK_SEL5[2:0]
Rsvd
00AA
Rsvd
CLK_SEL7[2:0]
Rsvd
00AB
10
10
Rsvd
D1
D0
0
0
CLK_SEL4[2:0]
CLK_SEL6[2:0]
Rsvd
Bit Field Name
PLL_SYN
CLK_SEL4[2:0]
CLK_SEL5[2:0]
Output Clock Source Control Register Block Field Descriptions
Field Type Default Value Description
Output Synchronization Control for Outputs Derived from PLL
Setting this bit from 01 will cause the output divider(s) for the affected outputs to be
R/W
0b
held in reset.
Setting this bit from 10 will release all the output divider(s) for the affected outputs to
run from the same point in time with the coarse output phase adjustment reset to 0.
Clock Source Selection for output Q4, nQ4: Do not select Input Reference 0 or 1 if that
input is faster than 250MHz
000 = PLL
001 = Reserved
R/W
000b
010 = Output Q2, nQ2
011 = Output Q3, nQ3
100 = Input Reference 0 (CLK0)
101 = Input Reference 1 (CLK1)
110 = Reserved
111 = Crystal Input
Clock Source Selection for output Q5, nQ5: Do not select Input Reference 0 or 1 if that
input is faster than 250MHz
000 = PLL
001 = Reserved
R/W
010b
010 = Output Q2, nQ2
011 = Output Q3, nQ3
100 = Input Reference 0 (CLK0)
101 = Input Reference 1 (CLK1)
110 = Reserved
111 = Crystal Input
REVISION 4 07/08/15
25
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