8T49N240 Datasheet, PDF (25/76 Pages) Integrated Device Technology – FemtoClock NG Ultra-Performance

8T49N240 Datasheet
Table 12. GPIO Control Register Bit Field Locations and Descriptions
The values observed on any GPIO pins that are used as general purpose inputs are visible in the GPI[3:0] register that is located at
location 0x020C near a number of other read-only registers.
Address (Hex)
0030
0031
0032
0033
0034
0035
0036
0037
0038
Bit Field Name
GPIO_DIR[3:0]
GPI3SEL[2:0]
GPI2SEL[2:0]
GPIO Control Register Block Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
Rsvd
GPIO_DIR[3:0]
Rsvd
GPI3SEL[2] GPI2SEL[2] GPI1SEL[2] GPI0SEL[2]
Rsvd
GPI3SEL[1] GPI2SEL[1] GPI1SEL[1] GPI0SEL[1]
Rsvd
GPI3SEL[0] GPI2SEL[0] GPI1SEL[0] GPI0SEL[0]
Rsvd
GPO3SEL[2] GPO2SEL[2] GPO1SEL[2] GPO0SEL[2]
Rsvd
GPO3SEL[1] GPO2SEL[1] GPO1SEL[1] GPO0SEL[1]
Rsvd
GPO3SEL[0] GPO2SEL[0] GPO1SEL[0] GPO0SEL[0]
Rsvd
Rsvd
GPO[3:0]
GPIO Control Register Block Field Descriptions
Field
Type Default Value
Description
R/W
0000b Direction control for General-Purpose I/O Pins GPIO[3:0]:
0 = input mode
1 = output mode
R/W
001b
Function of GPIO[3] pin when set to input mode by GPIO_DIR[3] register bit:
000 = General Purpose Input (value on GPIO[3] pin directly reflected in GPI[3] register
bit)
001 = reserved
010 = reserved
011 = reserved
100 through 111 = reserved
R/W
001b
Function of GPIO[2] pin when set to input mode by GPIO_DIR[2] register bit:
000 = General Purpose Input (value on GPIO[2] pin directly reflected in GPI[2] register
bit)
001 = CSEL: Manual Clock Select Input for PLL
010 = reserved
011 = reserved
100 = reserved
101 through 111 = reserved
©2017 Integrated Device Technology, Inc.
25
May 31, 2017