IDT77155 Datasheet, PDF (24/50 Pages) Integrated Device Technology – PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS

IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
RECEIVE LINE OVERHEAD STATUS REGISTER
ADDRESS 0X18
DEFAULT = 8’B00000000
Bit
Bit 7
Type
R/W
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
R
Bit 0
R
Symbol
B2Word
—
—
—
—
—
LAIS
LRDI
Function
Controls accumulation of B2 errors. If set to logic one, the B2 error counter
is incremented only once per frame for one or more errors received during
that frame. When disabled, the B2 error counter is incremented by the
received error count during that frame. Max B2 errors is 8 per frame for
STS-1 and 24 for STS-3c per frame.
Reserved
Reserved
Reserved
Reserved
Reserved
Receive line alarm signal status indication.
Receive line remote defect indication status indication.
RECEIVE LINE OVERHEAD INTERRUPT REGISTER
ADDRESS 0X19
DEFAULT = 8’B0000XXXX
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R
R
R
R
Symbol
LFEBEIEn
B2ErrIEn
LAISIEn
LRDIIEn
LFEBEInt
B2ErrInt
LAISInt
LRDIInt
Function
Receive line FEBE (Z2) error interrupt enable. If set to logic one, an
interrupt is generated if a line FEBE is detected.
Receive line BIP (B2) error interrupt enable. If set to logic one, an
interrupt is generated if a line BIP (B2) error is detected.
Receive line alarm indication signal interrupt enable. If set to logic one, an
interrupt is generated if LAIS changes state.
Receive line RDI error interrupt enable. If set to logic one, an interrupt is
generated if line RDI signal changes state.
Receive line FEBE (Z2) error interrupt is asserted when a line FEBE
is detected. Cleared when this register is read.
Receive line BIP error interrupt is asserted when a B2 error is detected.
Cleared when this register is read.
Receive line alarm interrupt is asserted when a change in the line alarm
signal (LAIS) occurs. Cleared when this register is read.
Receive line RDI interrupt is asserted when a change in the line RDI
signal occurs. Cleared when this register is read.
RECEIVE LINE OVERHEAD BIP ERROR COUNTER
DEFAULT = 20’HXXXXX
ADDRESS 0X1A
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
B2ErrCnt[7]
B2ErrCnt[6]
B2ErrCnt[5]
B2ErrCnt[4]
B2ErrCnt[3]
B2ErrCnt[2]
B2ErrCnt[1]
B2ErrCnt[0]
Function
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
8.03
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