ADC1113D125 Datasheet, PDF (23/39 Pages) NXP Semiconductors – Dual 11-bit ADC; serial JESD204A interface

Integrated Device Technology
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
The steps involved in a data transfer are as follows:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
CS
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Fig 23. Transfer diagram for two data bytes (3-wire type)
Register N (data)
Register N + 1 (data)
005aaa086
11.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel receives the next
SPI-instruction. By default the channel A and B receives the same instructions in write
mode. In read mode only A is active.
ADC1113D125 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
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