8T39S08A Datasheet, PDF (23/39 Pages) Integrated Device Technology – Crystal or Differential-to-Differential Clock Fanout Buffer

8T39S08A Datasheet
2.5V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HSTL, HCSL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 6A to 6E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 6A, the input
termination applies for IDT open emitter HSTL drivers. If you are
using an HSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
HSTL
IDT Open Emitter
HSTL Driver
2.5V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 6A. CLK/nCLK Input Driven by an
IDT Open Emitter HSTL Driver
Figure 6C. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 6B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
2.5V
2.5V
*R3 33
Zo = 50
Zo = 50
*R4 33
HCSL
R1
50
*Optional – R3 and R4 can be 0
CLK
nCLK
R2
50
Differential
Input
Figure 6D. CLK/nCLK Input Driven by a
2.5V HCSL Driver
Figure 6E. CLK/nCLK Input Driven by a 2.5V LVDS Driver
©2016 Integrated Device Technology, Inc.
23
May 19, 2016