5P49V5908_16 Datasheet, PDF (23/30 Pages) Integrated Device Technology – Programmable Clock Generator

5P49V5908 DATASHEET
LVPECL Driver
Figure General Diagram for LVPECL Driver to XTAL Input
Interface shows an example of the interface diagram for a
+3.3V LVPECL driver. This is a standard LVPECL termination
with one side of the driver feeding the XIN/REF input. It is
recommended that all components in the schematics be
placed in the layout; though some components might not be
used, they can be utilized for debugging purposes. The
datasheet specifications are characterized and guaranteed by
using a quartz crystal as the input. If the driver is 2.5V
LVPECL, the only change necessary is to use the appropriate
value of R3.
Z o = 50 Ohm
Z o = 50 Ohm
+3.3V LVPECL Dr iv er
R1 R 2
50 50
R3
50
XOUT
C1
0. 1 uF
XIN / REF
Table 25 Nominal Voltage Divider Values vs Driver VDD
shows resistor values that ensure the maximum drive level for
the CLKIN port is not exceeded for all combinations of 5%
tolerance on the driver VDD, the VersaClock Vddo_0 and 5%
resistor tolerances. The values of the resistors can be
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the impedance of the R1-R2
divider. To assist this assessment, the total load on the driver
is included in the table.
Table 25: Nominal Voltage Divider Values vs Driver VDD
LVCMOS Driver VDD Ro+Rs
R1
3.3
50.0
130
2.5
50.0
100
1.8
50.0
62
R2
Vrx (peak)
75
0.97
100
1.00
130
0.97
Ro+Rs+R1+R2
255
250
242
NOVEMBER 11, 2016
23
PROGRAMMABLE CLOCK GENERATOR