IDT72V2103 Datasheet, PDF (22/46 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO

IIDDTT7722VV226130/32/7732/V228131/23933./31V03H/I1G1H3 3D.E3VNSHIITGYHSDUEPNESRITSYYNSCUPIIE^TMRNSAYRNRCOIIW^{TM BNUASRRFIOFWO} BUS FIFO
813K1x,01782, x161K8/x2692/1,184,432xK9,x296/21,81,4644Kx 1x89/5/1284,,218288Kx x9 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D =
262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Qn)
(Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for 9-
bit wide data.
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