5P49V5933 Datasheet, PDF (22/33 Pages) Integrated Device Technology – Generates up to two independent output frequencies

5P49V5933 PRELIMINARY DATASHEET
Wiring the Differential Input to Accept Single-Ended Levels
Figure Recommended Schematic for Wiring a Differential
Input to Accept Single-ended Levels shows how a differential
input can be wired to accept single ended levels. This
configuration has three properties; the total output impedance
of Ro and Rs matches the 50 ohm transmission line
impedance, the Vrx voltage is generated at the CLKIN inputs
which maintains the LVCMOS driver voltage level across the
transmission line for best S/N and the R1-R2 voltage divider
values ensure that Vrx p-p at CLKIN is less than the maximum
value of 1.2V.
V DD
Ro
Rs
Zo = 50 Ohm
Ro + Rs = 5 0
LV CMOS
R1
Vrx
R2
CLKI N
CLKI NB
Vers aCloc k 5 Rec eiver
Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Table 24 Nominal Voltage Divider Values vs Driver VDD
shows resistor values that ensure the maximum drive level for
the CLKIN port is not exceeded for all combinations of 5%
tolerance on the driver VDD, the VersaClock Vddo_0 and 5%
resistor tolerances. The values of the resistors can be
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the impedance of the R1-R2
divider. To assist this assessment, the total load on the driver
is included in the table.
Table 24: Nominal Voltage Divider Values vs Driver VDD
LVCMOS Driver VDD Ro+Rs
R1
R2
3.3
50.0
130
75
2.5
50.0
100
100
1.8
50.0
62
130
HCSL Differential Clock Input Interface
CLKIN/CLKINB will accept DC coupled HCSL signals.
Vrx (peak)
0.97
1.00
0.97
Ro+Rs+R1+R2
255
250
242
Zo=50ohm
Q
Zo=50ohm
nQ
CLKIN
CLKINB
VersaClock 5 Receiver
CLKIN, CLKINB Input Driven by an HCSL Driver
PROGRAMMABLE CLOCK GENERATOR
22
REVISION B 07/13/15