92HD99B Datasheet, PDF (216/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Address
Channel RIGHT Coefficients (24bit)
Channel LEFT Coefficients (24bit)
EQRAM
Bits
0x14
0x15
[47:24]
EQ_COEF_F4_B0
EQ_COEF_F4_B1
[23:00]
EQ_COEF_F4_B0
EQ_COEF_F4_B1
0x16
EQ_COEF_F4_B2
EQ_COEF_F4_B2
0x17
EQ_COEF_F4_A1
EQ_COEF_F4_A1
0x18
EQ_COEF_F4_A2
EQ_COEF_F4_A2
0x19
0x1A
0x1B
0x1C
0x1D
EQ_PRESCALE
EQ_PRESCALE
based on 48Khz sample rate
EQ_COEF_F0_B0
EQ_COEF_F0_B0
EQ_COEF_F0_B1
EQ_COEF_F0_B1
EQ_COEF_F0_B2
EQ_COEF_F0_B2
EQ_COEF_F0_A1
EQ_COEF_F0_A1
0x1E
EQ_COEF_F0_A2
EQ_COEF_F0_A2
0x1F
EQ_COEF_F1_B0
EQ_COEF_F1_B0
0x20
EQ_COEF_F1_B1
EQ_COEF_F1_B1
0x21
0x22
0x23
0x24
0x25
0x26
EQ_COEF_F1_B2
EQ_COEF_F1_A1
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
EQ_COEF_F1_B2
EQ_COEF_F1_A1
EQ_COEF_F1_A2
EQ_COEF_F2_B0
EQ_COEF_F2_B1
EQ_COEF_F2_B2
0x27
EQ_COEF_F2_A1
EQ_COEF_F2_A1
0x28
EQ_COEF_F2_A2
EQ_COEF_F2_A2
0x29
EQ_COEF_F3_B0
EQ_COEF_F3_B0
0x2A
EQ_COEF_F3_B1
EQ_COEF_F3_B1
0x2B
0x2C
0x2D
0x2E
0x2F
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
EQ_COEF_F3_B2
EQ_COEF_F3_A1
EQ_COEF_F3_A2
EQ_COEF_F4_B0
EQ_COEF_F4_B1
0x30
EQ_COEF_F4_B2
EQ_COEF_F4_B2
0x31
EQ_COEF_F4_A1
EQ_COEF_F4_A1
0x32
EQ_COEF_F4_A2
EQ_COEF_F4_A2
0x33
EQ_PRESCALE
EQ_PRESCALE
The EQRAM is programmed indirectly through the Control Bus in the following manner:
1) Write the 48-bit write data to the EQRAM_WRITE register
2) Write the target address to the EQ_ADDRESS register
3) Set bit 7 of the EQRAM_CTRL register
The write will occur when the EQRAM is not being accessed by the DSP audio processing routines. When complete
the hardware will automatically clear this bit.
Reading back from the EQRAM is done in the following manner:
1) Write target address to EQ_ADDR register
2) Set bit 6 of the EQRAM_CTRL register
When the hardware completes the read it will automatically clear this bit.
3) When bit 6 of the EQRAM_CTRL register has been cleared, read the 48bit data from the EQRAM_READ register.
IDT CONFIDENTIAL
216
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.2 1/12
92HD99