92HD99B Datasheet, PDF (210/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.12. LMTCTRL Register
Control operation of the volume Limiter (Compressor).
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
verb F88/788
Bit
Label
7:4 –
3
zerocross
2:1 stepsize
0
limiter_en
Type Default
Description
RO 0
Reserved for future use.
RW 0
1 = only change limiter gain value on zero cross.
RW 0
Gain stepsize when incrementing or decrementing:
0 - 0.75 dB, 1 - 1.5 dB, 2 - 3.0 dB, 3 - 6.0 dB
RW 0
1 = enable limiter (compressor)
7.29.1.13. LMTATKTIME (0x19), LMTHOLDTIME (0x1A), LMTRELTIME (0x1B) Registers
These 8-bit registers set the timer values between incrementing/decrementing the Compressor attenuation values. There is
one register each for Attack, Hold, and Release times, the configuration parameters are the same for all three and are
shown in the table below.
Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing to NID22h verb
77F will cause reset on all silicon revisions..
Register Address
verb F89/789
Bit
Label
7
ATK10ms
6:0 LMTAT[6:0]
Type Default
Description
RW 0
1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
RW 0
Timer value in units of 1 or 10ms.
Register Address
verb F8A/78A
Bit
Label
7
HOLD10ms
6:0 LMTHT[6:0]
Type Default
Description
RW 0
1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
RW 0
Timer value in units of 1 or 10ms.
Register Address
verb F8B/78B
Bit
Label
7
REL10ms
6:0 LMTRT[6:0]
Type Default
Description
RW 0
1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
RW 0
Timer value in units of 1 or 10ms.
7.29.1.14. LMTATKTH (0x1D–LO, 0x1C–HI), LMTRELTH (0x1F–LO, 0x1E–HI) Registers
These 16-bit registers set the threshold values. When in attack phase and the Attack Threshold is exceeded the
Compressor attenuation is incremented by stepsize (see LMTCTRL). When in release phase and the Release Threshold is
not exceeded the Compressor attenuation is incremented by stepsize (but not above 0)
Prior to WC revision, these registers reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing to NID22h verb
77F will cause reset on all silicon revisions..
Register Address
verb F8C/78C
Bit
Label
7:0 LATKTH[15:8]
Type Default
Description
RW 7F
8’hFF would equal threshold level of +2.0dB. Each step below
this 8-bit full scale value reduces threshold level by 0.0078 dB.
IDT CONFIDENTIAL
210
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.2 1/12
92HD99