IDT72V36106 Datasheet, PDF (21/39 Pages) Integrated Device Technology – 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO^TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA ₄
MRS1,
MRS2
tFSS
FS2
tFSS
FS1,FS0
0,0
tFSH
tFSH
FFA/IRA
tWFF
tENS2
tENH
tSKEW1 ⁽¹⁾
ENA
A0-A35
CLKC
tDS
tDH
AFA Offset
(Y1)
AEB Offset
(X1)
AFC Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
1
2
tWFF
FFC/IRC
4676 drw10
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
FS2
FFA/IRA
FS1/SEN
FS0/SD⁽³⁾
tFSS
tFSS
CLKC
4
tFSH
tSPH
tSENS
tSENH
tSDS
tSDH
AFA Offset
(Y1) MSB
tSENS
tSKEW(1)
tSENH
tSDS
tSDH
AEA Offset
(X2) LSB
tWFF
FFC/IRC
tWFF
4676 drw11
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
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