IDT72261 Datasheet, PDF (21/30 Pages) Integrated Device Technology – CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9

IDT72261/72271 SyncFIFO™
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
SEN
LD
tENS
tLDS
tDS
tENH
tLDH
tENH
tLDH
SI
BIT 0
BIT 7
BIT 0
(1)
BIT X
BIT 0
BIT 7
BIT 0
(1)
BIT X
NOTE:
1. For the 72261, X = 5.
For the 72271, X = 6.
EMPTY
OFFSET (LSB)
EMPTY OFFSET (MSB)
FULL OFFSET (LSB)
FULL OFFSET
(MSB)
Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
3036 drw 14
WCLK
LD
WEN
D0 - D8
tCLK
tCLKH
tCLKL
tLDS
tLDH
tENS
tDS
tENH
tDH
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
Figure 12. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
3036 drw 15
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