89HPES64H16AG2 Datasheet, PDF (21/62 Pages) Integrated Device Technology – Low latency cut-through architecture

IDT 89HPES64H16AG2 Data Sheet
Function
Pin Name Type Buffer
I/O
Type
Internal
Resistor¹
General Purpose I/O
System Pins
EJTAG / JTAG
SerDes Reference
Resistors
GPIO[53:0]
CLKMODE[1:0]
CLKMODE[2]
GCLKFSEL
MSMBSMODE
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1011MERGEN
P1213MERGEN
P1415MERGEN
PERSTN
RSTHALT
SWMODE[3:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
REFRES[15:0]
REFRESPLL
I/O
LVTTL
STI,
pull-up
High Drive
I
LVTTL
Input
pull-up
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
STI
I
Input
pull-down
I
pull-down
I
LVTTL
STI
pull-up
I
STI
pull-up
O
I
STI
pull-up
I
STI
pull-up
I/O
Analog
I/O
Table 9 Pin Characteristics (Part 3 of 3)
1. _{Internal resistor values under typical operating conditions are 92K Ω for pull-up and 91K Ω for pull-down.}
2. _{All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.}
3. _{Schmitt Trigger Input (STI).}
Notes
21 of 62
November 28, 2011