92HD99B Datasheet, PDF (209/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.9. PWM2 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
verb F85/785
Bit
7:2
1
0
Label
dvalue
pwm_outflip
pwm_outmode
Type Default
Description
RW 0x10 dvalue constant field.
RW 0
1= swap pwm a/b output pair for all channels
RW 1
1= tristate, 0 = binary
7.29.1.10. PWM1Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
Bit
Label
7
Reserved
verb F86/786
6:2 dithpos
1
dither_range
0
dithclr
Type Default
Description
RO 0
RESERVED
RW 0
Dither position, where dither inserted after NS
0,1,2 = dither bits 2:0
4 = dither bits 3:1
5 = dither bits 4:1
...
19 = dither bits 19:17
RW 0
1= dither -1 to +1, 0 = dither -3 to +3
RW 0
1 = disable dither
7.29.1.11. PWM0 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
Bit
Label
7:6 PhaseOffset
verb F87/787
5
clk320mode
4
roundup
3
bfclr
2
fourthorder
1
add3_sel
0
Btl_test_mode
Type Default
Description
RW 01
PWM ch1 offset from ch0 at 8x sample rate by:
00 = 0 degrees
01 = 90 degrees
10 = 180 degrees
11 = NA
R1
1 = PCA clock 320 mode
0 = PCA clock 294 mode
RW 1
1= roundup, 0 = truncate for quantizer
RW 0
1 = disable binomial filter
RW 0
1 = fourth order binomial filter, 0 = 3rd order binomial filter
RW 0
1 = 24-bit Noise Shaper output (pre-quantizer), 0 = 8/9/10-bit
quantizer output
RW 0
1 = power stage test mode
IDT CONFIDENTIAL
209
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.2 1/12
92HD99