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92HD99B Datasheet, PDF (208/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM
92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.6. CONFIG Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
verb F82/782
Bit
Label
7
BPFBYP
6
PREBYP
5
EQBYP
4
BTL_dcbyp
3:1 Reserved
0
HPFBYP
Type Default
Description
RW 0
1= Bypass MonoOut band-pass filer
RW 1
1= Bypass BTL EQ filter prescale
RW 1
1= Bypass BTL EQ filter
RW 0
1 = bypass BTL DC filter
RO 0
RESERVED
RW 0
1= Bypass BTL high-pass filter (not DC removal filter)
7.29.1.7. PWM4 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
verb F83/783
Bit
Label
Type Default
Description
7
sc_status_clear_right RWC 0
Write once operation will clear sc_fault_status_right
6
sc_status_clear_left RWC 0
Write once operation will clear sc_fault_status_left
5
Reserved
RO 0
RESERVED
4
sc_Fault_status_right RO 0
1 = Fault occurs on right channel
3
sc_Fault_status_left RO 0
1 = Fault occurs on left channel
2:1 scdly_set
RW 00
Used for short circuit detection; designer will set the value
0
evenbit
RW 0
1=Noise Shaper output data are even
7.29.1.8. PWM3 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions.
Register Address
Bit
Label
verb F84/784
7:6 outctrl
5:0 cvalue
Type Default
Description
RW 0
pwm output muxing
0 = normal
1 = swap 0/1
2 = ch0 on both
3 = ch1 on both
RW 0x2
Tristate constant value filed, must be even and not 0
IDT CONFIDENTIAL
208
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.2 1/12
92HD99