92HD99B Datasheet, PDF (207/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.3. RESET Register
Register Address
verb F7F/77F
Bit
Label
7:0 RESET
Type Default
Description
RW 0
Writing causes registers to revert to their default values (similar
to a function group reset)
7.29.1.4. STATUS Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
Register Address
verb F80/780
Bit
Label
7
limit1latch
6
limit0latch
5:3 Reserved
2
limit1
1
limit0
0
zerodet_flag
Type Default
Description
RO 0
Latched version of limit1, clear via GAINCTRL_LO[7]
RO 0
Latched version of limit0, clear via GAINCTRL_LO[7]
RO 0x0
RESERVED
RO 0
Set (1) if regz saturation after gain multiply for CH1. may
change on a sample by sample basis.
RO 0
Set (1) if regz saturation after gain multiply for CH0. may
change on a sample by sample basis.
RO 0
Set when input zero detect of long string of zeroes.
7.29.1.5. INIT Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
Register Address
verb F81/781
Bit
Label
Type Default
Description
7:4 Reserved
RO 0
RESERVED
3
anabeep_dcbyp RW 0
1 = bypass analog Beep DC filter
2:1
anabeep_dc_coef
f
RW
0x2
0: dc_coef = 24’h004000;
1: dc_coef = 24’h001000;
2: dc_coef = 24’h000400;
3: dc_coef = 24’h000100;
0
Initialize
RW 0
1= Initialize/soft reset data path. Must be set when changing
the config0 or config1 registers.
IDT CONFIDENTIAL
207
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.2 1/12
92HD99