P9027LP-R Datasheet, PDF (20/27 Pages) Integrated Device Technology – Wireless Power Receiver

P9027LP-R Datasheet
0xD5 FLT_RAW_2
2
R
0xD5 FLT_RAW_1
1
R
0xD5 FLT_RAW_0
0
R
0 “1” when End Of Charge (EOC) pin is set.
0 Reserved
0 “1” when enable (E̅̅̅N̅) pin is set high.
Enabled fault flag. If the fault condition exists and this fault is enabled in Masked Fault Enable Register, the bit for the fault in FLT_MSKD will
be set.
Table 14. Masked Fault Condition
Byte
Address
0xD6
0xD6
0xD6
Byte Name
FLT_MSKD
FLT_MSKD
FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
0xD7 FLT_MSKD
Bit
Field
Typical
Default
Value
Description
7:5 R
0 Reserved.
4
R
0 Reserved.
3:0 R
0 Reserved
7
R
0 TS2 voltage is above programmed voltage. End of power transfer
packet sent (0x03) if triggered.
6
R
0
TS1 voltage is above programmed voltage. End of power transfer
packet sent (0x03) if triggered.
5
R
0 “1” when die temperature is greater than Tdie_shutdown. End of
power transfer packet sent (0x02) if triggered.
4
R
0 Reserved
3
R
0 Reserved
2
R
0 “1” when End of Charge (EOC) pin is set. End of power transfer
packet sent (0x01) if triggered.
1
R
0
R
0 Reserved
0 “1” when enable (E̅̅̅N̅) pin is set high. End of power transfer packet
sent (0x02) if triggered.
Enabled fault flag. If the fault condition exists and this fault is enabled in Masked Interrupt Enable Register, the bit for the fault in INTR_MSKD
will be set.
Table 15. Masked Interrupt Register
Byte
Address
0xD8
0xD8
0xD8
0xD9
Byte Name
INTR_MSKD
INTR_MSKD
INTR_MSKD
INTR_MSKD
Bit
Field
Typical
Default
Value
Description
7:5 R
0 Reserved.
4
R
0 Reserved.
3:0 R
0 Reserved
7
R
0 TS2 voltage is above programmed voltage, INT pin
will be toggled.
© 2016 Integrated Device Technology, Inc
20
April 28, 2016