8T49N241 Datasheet, PDF (20/64 Pages) Integrated Circuit Systems – Manual clock selection control input

8T49N241 DATA SHEET
Bit Field Name
ACQDAMP[2:0]
PLLGAIN[1:0]
SLEW[1:0]
HOLD[1:0]
HOLDAVG
FASTLCK
LOCK[7:0]
DSM_INT[8:0]
DSMFRAC[20:0]
DSM_ORD[1:0]
Digital PLL Feedback Configuration Register Block Field Descriptions
Field Type Default Value Description
Damping factor for Digital PLL while in acquisition (not locked):
000 = Reserved
001 = 1
010 = 2
R/W
011b
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
Digital Loop Filter Gain Settings for Digital PLL:
00 = 0.5
R/W
01b
01 = 1
10 = 1.5
11 = 2
Phase-slope control for Digital PLL:
00 = no limit - controlled by loop bandwidth of Digital PLL
R/W
00b
01 = 64us/s
10 = 11us/s
11 = Reserved
Holdover Averaging mode selection for Digital PLL:
00 = Instantaneous mode - uses historical value 100ms prior to entering holdover
R/W
00b
01 = Fast Average Mode
10 = Reserved
11 = Return to Center of VCO Tuning Range
Holdover Averaging Enable for Digital PLL:
R/W
0b
0 = Holdover averaging disabled
1 = Holdover averaging enabled as defined in HOLD[1:0]
Enables Fast Lock operation for Digital PLL:
R/W
0b
0 = Normal locking using LCKBW & LCKDAMP fields in all cases
1 = Fast Lock mode using ACQBW & ACQDAMP when not phase locked and
LCKBW & LCKDAMP once phase locked
Lock window size for Digital PLL. Unsigned 2’s complement binary number in steps
R/W
3Fh
of 2.5ns, giving a total range of 640ns. Do not program to 0.
R/W
02Dh
Integer portion of the Delta-Sigma Modulator value.
Fractional portion of Delta-Sigma Modulator value. Divide this number by 2²¹ to
R/W
000000h
determine the actual fraction.
Delta-Sigma Modulator Order for Digital PLL:
00 = Delta-Sigma Modulator disabled
R/W
11b
01 = 1st order modulation
10 = 2nd order modulation
11 = 3rd order modulation
FEMTOCLOCK^®NG UNIVERSAL FREQUENCY TRANSLATOR
20
REVISION 1 08/07/15