IDT77901C Datasheet, PDF (2/5 Pages) Integrated Device Technology – NICStAR Evaluation Board for IDT77201 PCI Segmentation and Reassembly Controller

IDT77901C/D
NICStAR Evaluation Board
ADVANCED INFORMATION
Commercial Temperature Range
probing into all buses and active signals lines for hardware
and/or software design, verification, and debugging opera-
tions.
FUNCTIONAL OVERVIEW
COMPATIBILITY AND CONFIGURATION
The board is designed for use in PCI systems, which may
include PC compatibles, MIPS, Alpha, Windows NT systems,
future PowerPC Macintosh systems, and so on. It supports
the 32 bit, 33 MHz, 5V part of the PCI spec, although this also
permits operation in a 64-bit, 33 MHz, 5V PCI slot.
OVERVIEW
The heart of the board is the IDT 77201 NICStAR, which is
an ATM Segmentation And Reassembly (SAR) controller.
The NICStAR connects directly to the PCI bus, a private
SRAM/EPROM bus, and the Utopia PHY interface. The PHY
device is an IDT77155. The PHY device connects in turn to a
Hewlett-Packard HFBR-5103 Optical Data Link (ODL) device
for the fiber optic connection. The ODL incorporates its own
fiber optic connectors.
THEORY OF OPERATION
The NICStAR has 50 signal pins which connect directly to
the PCI bus edge connector. 32 of these are multiplexed
address/data signals, and the remainder are control signals.
The NICStAR is compatible with the 5V, 33 MHz portion of the
PCI spec, so the eval board will work in motherboards with 32
or 64 bit, 5V, 33 MHz slots. The board will not work in 3.3V
slots.
The 77901 connects the PCI bus PRSNT1# and PRSNT2#
pins to ground; R59 (see schematic) is provided between the
PCI bus RST# signal and the NICStAR’s RST# input to
facilitate testing. This resistor is normally 0 Ohms but it could
be removed, and the pads used to insert some sort of AND
gate to allow the NICStAR to be reset without resetting the
host computer.
The NICStAR receives two clock input signals. One is from
the PCI bus, and this one can vary from DC to 33.333MHz. The
other is from a local oscillator on the 77901. U14 is the
NICStAR’s main clock: SAR_CLK. It runs typically at 50 MHz.
The rate of the Utopia interface, PHY_CLK is connected to a
FUNCTIONAL BLOCK DIAGRAM
8.09
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