ICS9148-20 Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – Pentium/ProTM System Clock Chip

ICS9148-20
Pin Descriptions
PIN NUM BER
1, 2, 47
3
4
5
6, 12, 18
7
8, 10, 11, 13, 14, 16,
17
9, 15
19, 33
20, 32
21
22, 23
24
PIN NAM E
REF (0:2)
GND1
X1
X2
GND2
P C IC L K _F
PCICLK (0:6)
VDD2
VDD
GND
VDD3
48M Hz (0:1)
GND3
25
S E L 1 0 0 /6 6 .6 #
26, 27
28
29
30
31
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
48
FS (0:1)
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
GNDL1
IOAPIC (0:1)
VDDL1
VDD1
TYPE
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
PWR
IN
IN
IN
IN
IN
IN
PWR
PWR
OUT
-
PWR
OUT
PWR
PWR
DESCRIPTION
14.318M Hz clock output
Ground for REF outputs
X TA L _IN 14.318M H z C rystal input, has internal 33pF
load cap and feed back resistor from X2
X TA L _O U T C rystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48M Hz outputs, nominally 3.3V
48M Hz outputs
Ground for 48M Hz outputs
Select pin for enabling 100M Hz or 66.6M Hz
H=100M Hz, L=66.6M Hz (PCI always synchronous
33.3M Hz)
Frequency Select pins
Enables Spread Spectrum feature when LOW
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs @ 2.5V
Not internally connected
Ground for IOAPIC outputs
IOAPIC outputs (14.318M Hz) @ 2.5V
Power for IOAPIC outputs, nominally 2.5V
Supply for REF (0:1), X1, X2, nominal 3.3V
Select Functions
Functionality
Tristate
Testmode
Spread Spectrum
CPU
HI - Z
TCLK/2¹
Modulated²
PCI,
PCI_F
HI - Z
TCLK/6¹
Modulated²
REF
HI - Z
TCLK¹
14.318MHz
IOAPIC
HI - Z
TCLK¹
14.318MHz
48 MHz
Selection
HI - Z
TCLK/2¹
48.0MHz
SEL 100/66# FS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FS0
Function
0
Tri-State
1
(Reserved)
0
(Reserved)
1
Active 66.6MHz CPU, 33.3 PCI
0
Test Mode
1
(Reserved)
0
(Reserved)
1
Active 100MHz CPU, 33.3 PCI
Notes:
1. TCLK is a test clock driven on the X1 (crystal in
pin) input during test mode.
2. -0.5% modulation down spread from the selected
frequency.
2