ICS9147-12 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – Pentium/ProTM System and Cyrix™ Clock Chip

ICS9147-12
Pin Descriptions
PIN NUMBER
1
2
3, 10, 17, 24, 31,
31, 37, 43
4
5
6, 20,
7, 15
8
9, 11, 12, 13, 14, 16
18
19
21
22
23
25, 28,34
26, 27, 29, 30,
32, 33, 35, 36
38, 39, 41, 42
40, 46
44
45
47
48
PIN NAME
FS2
REF1
REF0
GND
X1
X2
N/C
VDD2
PCICLK_F
PCICLK (0:5)
FS0
FS1
VDD4
48MHz
24MHz
VDD3
SDRAM (0:7)
CPUCLK (0:3)
VDDL
PD#
IOAPIC
REF2
VDD1
TYPE
IN
OUT
OUT
PWR
IN
OUT
-
PWR
OUT
OUT
IN
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
OUT
OUT
PWR
DESCRIPTION
Latched input for frequency select2¹
Reference clock output
Reference clock output
Ground (common)
Crystal or reference input, nominally 14.318 MHz. Includes
internal load cap to GND and feedback resistor from X2.
Crystal output, includes internal load cap to GND.
Pins are not internally connected
Supply for PCICLK_F, and PCICLK (0:5)
Free running PCI clock
PCI clocks
Frequency select 0 input¹
Frequency select 1 input¹
Supply for 48MHz and 24MHz clocks
48MHz driver output for USB clock
24MHz driver output for Super I/O clock
Supply for SDRAM (0:7),
SDRAMs clock at CPU speed
CPUCLK clock output, powered by VDDL
Supply for CPUCLK (0:3) & IOAPIC
Power down stops all clocks low and disables oscillator and
internal VCO’s.²
IOAPIC clock output, powered by VDDL at crystal frequency
Reference clock output.
Supply for REF (0:2), X1, X2
Note 1: Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs.
Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie
VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input
series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD#
pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100Ω series resistor will be suffcient.
2