ICS8S89832I Datasheet, PDF (2/16 Pages) Integrated Device Technology – Four differential LVDS output pairs

ICS8S89832I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
15, 16
V_DD
EN
nIN
V_{REF_AC}
V_T
IN
GND
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is V_DD/2V. Includes a
37kΩ pullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. See Table 3A
LVTTL / LVCMOS interface levels.
Inverting differential clock input. 50Ω internal input termination to V_T.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting differential clock input. 50Ω internal input termination to V_T.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
Maximum
Units
pF
kΩ
ICS8S89832AKI REVISION A JANUARY 11, 2010
2
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