ICS874003-02 Datasheet, PDF (2/14 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 20
QA1, nQA1 Output
Differential output pair. LVDS interface levels.
2, 19
3, 4
5
6,
9,
16
7
V
DDO
QA0, nQA0
MR
F_SEL0,
F_SEL1,
F_SEL2
nc
Power
Output
Input
Input
Output supply pins.
Pulldown
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown
Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs.
LVCMOS/LVTTL interface levels.
Unused
No connect.
8
V_DDA
Power
Analog supply pin.
10
V_DD
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
11
OEA
Input Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
12
CLK
Input Pulldown Non-inverting differential clock input.
13
nCLK
Input Pullup Inverting differential clock input.
14
15
17, 18
GND
OEB
nQB0, QB0
Power
Input
Output
Pullup
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
TABLE 3. OUTPUT ENABLE FUNCTION TABLE
Inputs
OEA OEB
0
0
1
1
Outputs
QA0/nQA0, QA1/nQA1
HiZ
Enabled
QB0/nQB0
HiZ
Enabled
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT^™ / ICS^™ PCI EXPRESS™ JITTER ATTENUATOR
2
ICS874003AG-02 REV A AUGUST 29, 2006