ICS8545-02 Datasheet, PDF (2/13 Pages) Integrated Device Technology – LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER

ICS8545-02
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
Name
GND
CLK_EN
CLK_SEL
Type
Power
Input
Pullup
Input Pulldown
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
4
CLK1
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 7
6
8
10, 18
11, 12
14, 15
16, 17
19, 20
nc
CLK2
OE
V_DD
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Unused
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
No connect.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT™ / ICS™ LVDS FANOUT BUFFER
2
ICS8545AG-02 REV. A March 3, 2009