ICS853S12I Datasheet, PDF (2/17 Pages) Integrated Device Technology – Maximum output frequency

ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q11, nQ11 Output
Differential output pair. LVPECL interface levels.
3, 6
V
Power
EE
Negative supply pins.
4
PCLK
Input Pulldown Non-inverting differential clock input.
5
nPCLK
Input
Pullup/
Pulldown
Inverting differential clock input.
7, 8
Q0, nQ0
Output
Differential output pair. LVPECL interface levels.
9, 10
Q1, nQ1
Output
Differential output pair. LVPECL interface levels.
11, 16, 25, 30
12, 13
V_CC
Q2, nQ2
Power
Output
Positive supply pins.
Differential output pair. LVPECL interface levels.
14, 15
Q3, nQ3
Output
Differential output pair. LVPECL interface levels.
17, 18
Q4, nQ4
Output
Differential output pair. LVPECL interface levels.
19, 20
Q5, nQ5
Output
Differential output pair. LVPECL interface levels..
21, 22
Q6, nQ6
Output
Differential output pair. LVPECL interface levels.
23, 24
Q7, nQ7
Output
Differential output pair. LVPECL interface levels.
28, 29
Q9, nQ9
Output
Differential output pair. LVPECL interface levels.
26, 27
Q8, nQ8
Output
Differential output pair. LVPECL interface levels.
31, 32
Q10, nQ10 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
PCLK
nPCLK
Outputs
Q0:Q11
nQ0:nQ11
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels".
IDT^™ / ICS^™ LVPECL FANOUT BUFFER
2
ICS853S12AKI REV. A MAY 21, 2008