ICS844002 Datasheet, PDF (2/16 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 7
nc
Unused
No connect.
2, 20
3, 4
V_DDO
Q0, nQ0
Power
Ouput
Output supply pins.
Differential output pair. LVDS interface levels.
5
6
8
9, 11
MR
nPLL_SEL
V_DDA
F_SEL0,
F_SEL1
Input
Input
Power
Input
Pulldown
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
10
12, 13
V_DD
XTAL_OUT,
XTAL_IN
Power
Input
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
14
REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input.
Selects between crystal or REF_CLK inputs as the the PLL Reference
15
nXTAL_SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
16
nc
Unused
No connect.
17
GND
Power
Power supply ground.
18, 19
nQ1, Q1 Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT^™ / ICS^™ LVDS FREQUENCY SYNTHESIZER
2
ICS844002AG REV. A SEPTEMBER 28, 2007