ICS843204I Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS843204I
FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
3, 4
5, 10, 11, 12,
13, 20, 25, 26,
27, 28, 29, 37,
38, 44
6
7
8
9
14,
15
16, 47
nQA0, QA0
Output
nc
Unused
V_{CCO_A}
SELA1
Power
Input
SELA0
Input
nPLL_BYPASS_A
XTAL_IN1,
XTAL_OUT1
CLK1, CLK0
Input
Input
Input
Differential output pair. LVPECL interface levels.
No connect.
Pulldown
Pulldown
Pullup
Pulldown
Output supply pin for Bank A outputs.
Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
When LOW, PLL is bypassed. When HIGH, PLL output is active.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
LVCMOS/LVTTL clock inputs.
21, 22
QB0, nQB0
Ouput
Differential output pair. LVPECL interface levels.
17
IN_SEL_B
Input
Pullup
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects
CLK1 input. LVCMOS/LVTTL interface levels.
18
nPLL_BYPASS_B Input
Pullup
When LOW, PLL is bypassed. When HIGH, PLL output is active.
LVCMOS/LVTTL interface levels.
19
23, 24
V_{CCO_B}
QB1, nQB1
Power
Ouput
Output supply pin for Bank B outputs.
Differential output pair. LVPECL interface levels.
31
SELB1
Input
Pullup
Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW,
selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels.
30
32, 40
33
V_{CCA_B}
V_CC
OEB1
Power
Power
Input
Pullup
Analog supply pin for Bank B outputs.
Core supply pins.
Output enable pin. When HIGH, QB1/nQB1 outputs are enable.
LVCMOS/LVTTL interface levels.
34
OEB0
Input
Pullup
Output enable pin. When HIGH, QB0/nQB0 outputs are enabled.
LVCMOS/LVTTL interface levels.
35, 43
36
V_EE
SELB0
Power
Input
Pullup
Negative supply pins.
Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW,
selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels.
39
V_{CCA_A}
Power
Analog supply pin for Bank A outputs.
41
OEA1
Input
Pullup
Output enable pin. When HIGH, QA1/nQA1 outputs are enabled.
LVCMOS/LVTTL interface levels.
42
OEA0
Input
Pullup
Output enable pin. When HIGH, QA0/nQA0 outputs are enabled.
LVCMOS/LVTTL interface levels.
45,
46
XTAL_OUT0,
XTAL_IN0
Input
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
48
IN_SEL_A
Input
Pullup
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects
CLK0 input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C_IN
R_PULLDOWN
R_PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT^™ / ICS^™ 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843204AGI REV. A MARCH 18, 2009