ICS542MLFT Datasheet, PDF (2/6 Pages) Integrated Device Technology – CLOCK DIVIDER

ICS542
CLOCK DIVIDER
Pin Assignment
ICLK 1
VDD 2
GND 3
S0 4
8 CLK
7 CLK/2
6 OE
5 S1
8-pin (150 mil) SOIC
CLOCK DIVIDER
Clock Decoding Table
S1 S0
CLK
CLK/2
00
Power Down All
01
Input/6
Input/12
10
Input/8
Input/16
11
Input/2
Input/4
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
VDD
GND
S0
S1
OE
CLK/2
CLK
Pin
Type
XI
Power
Power
Input
Input
Input
Output
Output
Pin Description
Clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 0 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Select 1 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
Output Enable. Tri-states both output clocks when low. Internal pull-up
resistor.
Clock output per table above. Low skew divide by two of pin 8 clock.
Clock output per table above.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS542
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
IDT™ / ICS™ CLOCK DIVIDER
2
ICS542
REV J 051310