ADC1412D Datasheet, PDF (2/41 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

Integrated Device Technology
ADC1412D series
Dual 14-bit ADC: CMOS or LVDS DDR digital outputs
4. Ordering information
Table 1. Ordering information
Type number
f_s (Msps) Package
Name
Description
ADC1412D125HN-C1 125
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9  9  0.85 mm
ADC1412D105HN-C1 105
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9  9  0.85 mm
ADC1412D080HN-C1 80
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9  9  0.85 mm
ADC1412D065HN-C1 65
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9  9  0.85 mm
5. Block diagram
Version
SOT804-3
SOT804-3
SOT804-3
SOT804-3
ADC1412D
SDIO/ODS
SCLK/DFS
CS
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI INTERFACE
OTRA
INAP
INAM
CLKP
CLKM
INBP
INBM
T/H
INPUT
STAGE
ADC CORE
14-BIT
PIPELINED
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
T/H
INPUT
STAGE
ADC CORE
14-BIT
PIPELINED
ERROR
CORRECTION AND
DIGITAL
PROCESSING
OUTPUT
DRIVERS
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
CMOS:
DA13 to DA0
or
LVDS/DDR:
DA12_DA13_P to DA0_DA1_P,
DA12_DA13_M to DA0_DA1_M
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
CMOS:
DB13 to DB0
or
LVDS/DDR:
DB12_DB13_P to DB0_DB1_P
DB12_DB13_M to DB0_DB1_M
OTRB
CTRL
Fig 1. Block diagram
REFBT
REFBB
VCMB
SENSE
REFAB
REFAT
VCMA
VREF
005aaa096
ADC1412D_SER 5
Product data sheet
Rev. 05 — 2 July 2012
© IDT 2012. All rights reserved.
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