9ZXL1950_15 Datasheet, PDF (2/18 Pages) Integrated Device Technology – 19-output DB1900Z Low-Power Derivative w/85ohm Terminations

9ZXL1950 DATASHEET
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 ^DIF12#
GNDA 2
53 ^DIF12
^100M_133M# 3
52 ^VDDIO
^vHIBW_BYPM_LOBW# 4
51 ^GND
CKPWRGD_PD# 5
50 ^DIF11#
GND 6
49 ^DIF11
VDDR 7
48 ^DIF10#
DIF_IN 8
DIF_IN# 9
^SADR0_tri 10
SMBDAT 11
9ZXL1950
(epad should be connected to GND and is
pin 73)
47 ^DIF10
46 ^GND
45 ^VDD
44 ^DIF9#
SMBCLK 12
43 ^DIF9
^SADR1_tri 13
42 ^DIF8#
FBOUT_NC# 14
41 ^DIF8
FBOUT_NC 15
40 ^VDDIO
GND 16
39 ^GND
N/A 1530
DIF0 17
DIF0# 18
38 ^DIF7#
37 ^DIF7
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)
Power Management Table
Inputs
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
Control Bits
Outputs
SMBus
EN bit
X
0
1
DIFx/ FBOUT_NC/
DIFx# FB_OUT_NC#
Low/Low
Low/Low
Low/Low
Running
Running Running
PLL State
OFF
ON
ON
Power Connections
VDD
1
7
28, 45, 64
Pin Number
VDDIO
GND
2
6
21, 33, 40,
52, 57, 69
16, 22, 27, 34,
39, 46, 51, 58,
63, 70, 73
Description
Analog PLL
Analog Input
DIF clocks
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
(MHz)
100.00
133.33
DIFx
(MHz)
DIF_IN
DIF_IN
PLL Operating Mode
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 2
REVISION E 11/20/15