9ZXL1930 Datasheet, PDF (2/18 Pages) Integrated Device Technology – Fixed feedback path

9ZXL1930
19-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 ^DIF_12#
GNDA 2
53 DIF_12
100M_133M# 3
52 ^VDDIO
HIBW_BYPM_LOBW# 4
51 GND
CKPWRGD_PD# 5
50 ^DIF_11#
GND 6
49 ^DIF_11
VDDR 7
48 ^DIF_10#
DIF_IN 8
47 ^DIF_10
DIF_IN# 9
SMB_A0_tri 10
9ZXL1930
46 GND
45 ^VDD
SMBDAT 11
44 DIF_9#
SMBCLK 12
43 ^DIF_9
SMB_A1_tri 13
42 ^DIF_8#
FBOUT_NC# 14
41 DIF_8
FBOUT_NC 15
40 ^VDDIO
GND 16
39 GND
DIF_0 17
38 ^DIF_7#
DIF_0# 18
37 ^DIF_7
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Power Management Table
Inputs
CK PW RGD_PD#
0
1
D IF_IN/
DIF_IN#
X
Run ning
Control Bits
Outputs
SMBus
EN bit
X
0
1
DIF_ x/
DIF_x#
Low /Low
Low /Low
Ru nnin g
FBO UT_NC /
FB _OUT_NC#
L ow/Low
Running
Running
PLL State
OFF
ON
ON
Power Connections
VDD
1
7
28, 45, 64
Pin Number
VDDIO
GND
2
6
21, 33, 40,
52, 57, 69
16, 22, 27, 34,
39, 46, 51, 58,
63, 70
De scri ption
Analog PLL
Analog Input
D IF clocks
Functionality at Power-up (PLL mode)
100M _13 3M#
1
0
DIF_IN
(M Hz)
100. 00
133. 33
DIFx
(MHz)
DI F_IN
DI F_IN
PLL Operating Mode Table
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2 <V in< 1.8V
Vin > 2.2V
IDT® 19-OUTPUT LOW POWER DIFFERENTIAL ZBUFFER FOR PCIE GEN3 AND QPI
2
9ZXL1930
REV C 062614