9ZXL0831_16 Datasheet, PDF (2/18 Pages) Integrated Device Technology – 8-OUTPUT

9ZXL0831
8-OUTPUT DB800ZL
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
CKPWRGD_PD# 1
36 DIF_6#
GND 2
35 DIF_6
VDDR 3
34 VDD
DIF_IN 4
33 DIF_5#
DIF_IN# 5
9ZXL0831
32 DIF_5
SMBDAT 6
SMBCLK 7
Paddle is
pin 49
31 vOE5#
30 vOE4#
DFB_OUT_NC# 8
Connect to GND
29 DIF_4#
DFB_OUT_NC 9
28 DIF_4
VDD 10
27 VDD
vOE0# 11
26 DIF_3#
NC 12
25 DIF_3
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
Power Management Table
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
SMBus
EN bit
X
0
1
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
MHz
100.00
133.33
DIF(7:0)
DIF_IN
DIF_IN
Power Connections
Pin Number
VDD
44
3
10,15,19,
27,34,38, 42
GND
49
2
49
Description
Analog PLL
Analog Input
DIF clocks
SMBus Address
Address
1101100
+ Read/Write bit
x
DIF(7:0)/
DIF(7:0)#
Low/Low
Low/Low
Running
PLL STATE
IF NOT IN
BYPASS
MODE
OFF
ON
ON
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low
PLL Lo BW
Mid
High
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
IDT® 8-OUTPUT DB800ZL
2
9ZXL0831
REV E 081616