9FGU0831 Datasheet, PDF (2/16 Pages) Integrated Device Technology – Programmable Slew rate for each output

9FGU0831 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1
36 DIF5#
GNDXTAL 2
35 DIF5
XIN/CLKIN_25 3
34 vOE4#
X2 4
33 DIF4#
VDDXTAL1.5 5
32 DIF4
VDDREF1.5 6
vSADR/REF1.5 7
9FGU0831
31 VDDIO
30 VDDA1.5
GNDREF 8
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.5 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
vv prefix indicates internal 60KOhm pull down resistor
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
Power Management Table
CKPWRGD_PD#
SMBus
OE bit
OEx#
DIFx
REF
True O/P Comp. O/P
0
X
X
Low
Low
Hi-Z¹
1
1
0
Running
Running Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRGD_PD# is low, REF is Low.
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Connections
Pin Number
VDD
5
6
VDDIO
12
20,38
30
13,21,31,39,
47
GND
2
8
9
22,29,40
29
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
2
REVISION A 09/24/14