9FGU0441_16 Datasheet, PDF (2/15 Pages) Integrated Device Technology – 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator

9FGU0441 DATASHEET
Pin Configuration
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL1.5 4
VDDREF1.5 5
vSADR/REF1.5 6
GNDREF 7
GNDDIG ₈
32 31 30 29 28 27 26 25
9FGU0441
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.5
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
SMBus
DIFx
OE bit OEx# True O/P Comp. O/P
REF
0
X
X
Low
Low
Hi-Z¹
1
1
0
Running
Running Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
2
OCTOBER 18, 2016