9FGU0231 Datasheet, PDF (2/15 Pages) Integrated Device Technology – Programmable output amplitude

9FGU0231 DATASHEET
Pin Configuration
XIN/CLKIN_25 1
X2 2
VDDXTAL1.5 3
vSADR/REF1.5 4
GNDREF 5
GNDDIG ₆
24 23 22 21 20 19
18 DIF1#
17 DIF1
9FGU0231
16 VDDA1.5
15 GNDA
14 DIF0#
13 DIF0
7 8 9 10 11 12
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
SMBus
OE bit
X
1
0
DIFx
True O/P Comp. O/P
Low
Low
Running
Running
Low
Low
REF
Hi-Z¹
Running
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,
when CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
3
7
11,20
16
GND
5,24
6
10,21
15
Description
XTAL, REF
Digital
DIF outputs
PLL Analog
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
2
REVISION A 09/24/14